tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 420

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

INTSBI interrupt
Fig. 15.7.2.2 Transmit Data Retention Time at the End of Transmission
8-bit receive mode
Set the control register to the receive mode. Then writing "1" to SBI0CR1 <SIOS> enables
reception. Data is taken into the shift register from the SI pin, with the least-significant bit
(LSB) first, in synchronization with the serial clock. Once the shift register is loaded with
the 8-bit data, it transfers the received data to SBI0DBR and the INTSBI (buffer-full)
interrupt request is generated to request reading the received data. The interrupt service
program then reads the received data from SBI0DBR.
In the internal clock mode, the serial clock will be stopped and automatically be in the wait
state until the received data is read from SBIDBR.
In the external clock mode, shift operations are executed in synchronization with the
external clock. The maximum data transfer rate varies, depending on the maximum
latency between generating the interrupt request and reading the received data.
Reception can be terminated by clearing <SIOS> to "0" or setting <SIOINH> to "1" in the
INTSBI interrupt service program. If <SIOS> is cleared, reception continues until all the
bits of received data are written to SBI0DBR. The program checks SBI0SR <SIOF> to
determine whether reception has come to an end. <SIOF> is cleared to "0" at the end of
reception. After confirming the completion of the reception, last received data is read. If
<SIOINH> is set to "1," the reception is aborted immediately and <SIOF> is cleared to "0."
(The received data becomes invalid, and there is no need to read it out.)
SBI0CR1 ← 0 1 1 1 0 X X X
SBI0CR1 ← 1 0 1 1 0 0 0 0
Reg.
(Note) The contents of SBI0DBR will not be retained after the transfer mode is
SCK pin
SIOF
SO pin
changed. The ongoing reception must be completed by clearing <SIOS> to
"0" and the last received data must be read before the transfer mode is
changed.
← SBI0DBR
7 6 5 4 3 2 1 0
bit 6
TMP19A61
(
rev1.0
Selects the receive mode.
Starts reception.
Reads the received data.
bit 7
)
-15-419
t
SODH
= Min. 4/f
sys
/2 [s]
TMP19A61