tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 501

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

21.4 Instructions Supported by the JTAG Controller Cells
(Note)
data input from terminal pin on ground that CPU is in operating state and make sure to execute the
test after the system reset is released
21.4.1 EXTEST instruction
This section describes the instructions supported by the JTAG controller cells of the TMP19A61.
When using EXTEST instruction, please note that malfunction may occur depending on the
The EXTEST instruction is used for external interconnect test. If this instruction is issued, the
BSR cells at output pins output test patterns in the Update-DR state, and the BSR cells at input
pins capture test results in the Capture-DR state.
Before the EXTEST instruction is selected, the boundary scan register is usually initialized using
the SAMPLE/PRELOAD instruction. If the boundary scan register has not been initialized, there
is the possibility that indeterminate data will be transmitted in the Update-DR state and bus
conflicts may occur between ICs. Fig. 21.8 shows the flow of data while the EXTEST instruction
is selected.
1.
2.
3.
4.
5.
6.
7.
8.
output pin.
Repeat steps 6 through 8 for each test pattern.
The basic external interconnect test procedure is as follows:
Input
TDI
Load the SAMPLE/PRELOAD instruction into the instruction register. This allows the
boundary scan register to be connected between TDI and TDO.
Initialize the boundary scan register by shifting in determinate data.
Initialize the TAP controller to put it in the Test-Logic-Reset state.
Load the initial test data into the boundary scan register.
Load the EXTEST instruction into the instruction register.
Capture the data applied to the input pin and input it into the boundary scan register.
Shift out the captured data while simultaneously shifting in the next test pattern.
Output the test pattern that was shifted into the boundary scan register for output to the
Fig. 21.8 Flow of Data While the EXTEST Instruction Is Selected
TMP19A61 (rev1.0)21-500
Boundary scan path
Internal logic
TMP19A61
Output
TDO