tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 23

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.
PLLSEL pin: to select frequency that adjusts to PLL depending on the clock frequency connected to X1,X2 pins
5.1 Operation Mode
5.2 Default Setting for System Clock
Clock/Standby Control
(I/O selective operation)
The system operation modes contain the standby modes in which the processor core operations are
stopped to reduce power consumption. Fig. 5.1 State Transition Diagram of Each Operation Mode is
shown below
IDLE mode
(CPU stop)
fosc
fpll
fc
fgear
fsys
fperiph : Clock frequency selected by SYSCR1<FPSEL> (Clock to be input to the
PLLSEL 1: 11-13.5MHz => 44-54MHz =====> 44-54MHz
: Clock frequency to be input via the X1 and X2 pins
: Clock frequency multiplied (quadrupled) by the PLL
: High-frequency clock frequency (clock frequency multiplied (quadrupled) by
0: 8-11 MHz => 64-88MHz =1/2=> 32-44MHz
Fig. 5.1 State Transition Diagram of Each Operation Mode
: Clock frequency selected by the system control register SYSCR1<GEAR2:0>
: System clock frequency
the PLL)
in the clock generator
The internal peripheral I/O operates according to the fsys/2 clock.
The CPU, ROM, RAM, DMAC and INTC all operate according to this clock.
peripheral I/O prescaler)
Clock mode without power supply to backup module
X1
Interrupt
Fig. 5.2 Default Setting for System Clock
Instruction
TMP19A61(rev 1.0)-5-22
PLL output
fperiph =fgear= fsys
fc = fpll = fosc×4
NORMAL mode
? fsys = fosc/2
fsys = fc/8
Reset
NORMAL mode
(fc/gear value)
Reset release
PLLSEL pin ( “H”or”L”)
Using PLL clock
Reset
Fc
Reset release
Instruction
Interrupt
(Entire circuit stop)
TMP19A61
STOP mode