tmp19a61f10xbg TOSHIBA Semiconductor CORPORATION, tmp19a61f10xbg Datasheet - Page 216

• Manufacturer Part Number: tmp19a61f10xbg
• Description: 32-bit Tx System Risc Tx19 Family
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Timing of Recovery Time Insertion (ALE width: 1fsys)
When read/write recovery is inserted (ALE width:1fsys)
fsys
A[23:16]
AD[15:0]
/RD /WR
ALE
/CS
Lower-order address
(4) Read and Write Recovery Time
A dummy cycle can be inserted in both a read and a write cycle. The dummy cycle
insertion setting can be made in the chip selector and wait controller registers,
BmnCS<BnWCV> (write recovery cycle) and <BnRCV> (read recovery cycle). As for the
number of dummy cycles, zero dummy cycle, one, two or four system clocks (internal) can
be specified for each block. Fig. 8.17 shows the timing of recovery time insertion.
If access to external areas occurs consecutively, a dummy cycle can be inserted for
recovery time.
Normal cycle
tsys
Higher-order address
Data
Fig. 8.17 Timing of Recovery Time Insertion
Lower-order address
TMP19A61(rev1.0)-8-215
1 recovery cycle
Higher-order address
Data
Dummy cycle
Lower-order address
Higher-order address
2 recovery cycles
TMP19A61
Data
Dummy cycle