s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 110

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM INSTRUCTION SET
SINGLE DATA TRANSFER (LDR, STR)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The
instruction encoding is shown in Figure 3-14.
The single data transfer instructions are used to load or store single bytes or words of data. The memory address
used in the transfer is calculated by adding an offset to or subtracting an offset from a base register.
The result of this calculation may be written back into the base register if auto-indexing is required.
3-28
31
Cond
28
27
01
26
25
I
24
P U
Figure 3-14. Single Data Transfer Instructions
23
22
B
[15:12] Source/Destination Registers
[19:16] Base Register
[20] Load/Store Bit
0 = Store to memory
1 = Load from memory
[21] Write-back Bit
0 = No write-back
1 = Write address into base
[22] Byte/Word Bit
0 = Transfer word quantity
1 = Transfer byte quantity
[23] Up/Down Bit
0 = Down: subtract offset from base
1 = Up: add offset to base
[24] Pre/Post Indexing Bit
0 = Post: add offset after transfer
1 = Pre: add offset before transfer
[25] Immediate Offset
0 = Offset is an immediate value
[11:0] Offset
[11:0] Unsigned 12-bit immediate offset
[3:0] Offset register [11:4] Shift applied to Rm
[31:28] Condition Field
11
11
21
W
20
L
19
Shift
Rn
Immediate
16
15
4 3
Rd
Rm
12
11
0
0
Offset
0
S3C2410A