s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 67

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
2
OVERVIEW
S3C2410A has been developed using the advanced ARM920T core, which has been designed by Advanced RISC
Machines, Ltd.
PROCESSOR OPERATING STATES
From the programmer's point of view, the ARM920T can be in one of two states:
SWITCHING STATE
Entering THUMB State
Entry into THUMB state can be achieved by executing a BX instruction with the state bit (bit 0) set in the operand
register.
Transition to THUMB state will also occur automatically on return from an exception (IRQ, FIQ, UNDEF, ABORT,
SWI etc.), if the exception was entered with the processor in THUMB state.
Entering ARM State
Entry into ARM state happens:
MEMORY FORMATS
ARM920T views memory as a linear collection of bytes numbered upwards from zero. Bytes 0 to 3 hold the first
stored word, bytes 4 to 7 the second and so on. ARM920T can treat words in memory as being stored either in Big-
Endian or Little-Endian format.
ARM state which executes 32-bit, word-aligned ARM instructions.
THUMB state which can execute 16-bit, halfword-aligned THUMB instructions. In this state, the PC uses bit 1 to
select between alternate halfwords.
Transition between these two states does not affect the processor mode or the contents of the registers.
On execution of the BX instruction with the state bit clear in the operand register.
On the processor taking an exception (IRQ, FIQ, RESET, UNDEF, ABORT, SWI etc.). In this case, the PC is
placed in the exception mode's link register, and execution commences at the exception's vector address.
PROGRAMMER'S MODEL
NOTE
PROGRAMMER'S MODEL
2-1