s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 520

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s3c2410a

Manufacturer Part Number
s3c2410a
Description
16/32-bit Risc Arm Microprocessor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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ELECTRICAL DATA
(V
NOTES:
1.
2.
(V
24-34
Vertical sync pulse width
Vertical back porch delay
Vertical front porch dealy
VCLK pulse width
VCLK pulse width high
VCLK pulse width low
Hsync setup to VCLK falling edge
VDEN set up to VCLK falling edge
VDEN hold from VCLK falling edge
VD setup to VCLK falling edge
VD hold from VCLK falling edge
LEND width
LEND hold from VCLK rising edge
VSYNC setup to HSYNC falling edge
VSYNC hold from HSYNC falling edge
IISLRCK delay time
IISDO delay time
IISDI Input Setup time
IISDI Input Hold time
CODEC clock frequency
DD
DD
HSYNC period
VCLK period
= 1.8V
= 1.8V
0.15 / 2.0 V
0.15 / 2.0 V
Parameter
Parameter
Table 24-11. TFT LCD Controller Module Signal Timing Constants
Table 24-12. IIS Controller Module Signal Timing Constants
0.1 V, T
0.1 V, T
A
A
= -40 to 85 C, V
= -40 to 85 C, V
Tde2csetup
Tvd2csetup
Tde2chold
Tl2csetup
Tvd2chold
Tf2hsetup
Tle2chold
Symbol
Tf2hhold
Tlewidth
Tvclkh
Tvspw
Tvbpd
Tvclkl
Tvfpd
Tvclk
EXT
EXT
Symbol
f
CODEC
t
t
t
t
LRCK
SDO
SDIS
SDIH
= 3.3V
= 3.3V
HBPD + HFPD +
HOZVAL + 3
VSPW + 1
HSPW + 1
VBPD+1
VFPD+1
Min
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.3V)
0.3V)
1
3
1/16
Min
0.7
0.8
6.2
0.1
Typ
Typ.
1
Max
16.3 / 15.3
Max
1.4
1.7
0.1
1
Phclk
Pvclk
Phclk
Phclk
Units
Pvclk
Pvclk
Pvclk
Pvclk
Pvclk
Pvclk
Pvclk
Pvclk
Pvclk
Pvclk
ns
S3C2410A
(note2)
(note1)
BLOCK
Unit
f
ns
ns
ns
ns
IIS_

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