s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 172

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

THUMB INSTRUCTION SET
FORMAT 11: SP-RELATIVE LOAD/STORE
OPERATION
The instructions in this group perform an SP-relative load or store. The THUMB assembler syntax is shown in the
following table.
NOTE:
4-26
L
0
1
The offset supplied in #Imm is a full 10-bit address, but must always be word-aligned (ie bits 1:0 set to 0),
since the assembler places #Imm >> 2 in the Word8 field.
STR Rd, [SP, #Imm]
LDR Rd, [SP, #Imm]
15
1
THUMB assembler
14
0
13
0
12
1
Table 4-12. SP-Relative Load/Store Instructions
11
L
STR Rd, [R13 #Imm]
LDR Rd, [R13 #Imm]
10
[7:0] Immediate Value
[10:8] Destination Register
[11] Load/Store Bit
0 = Store to memory
1 = Load from memory
ARM equivalent
Figure 4-12. Format 11
Rd
8
7
Add unsigned offset (255 words, 1020 bytes)
in Imm to the current value of the SP (R7).
Store the contents of Rd at the resulting
address.
Add unsigned offset (255 words, 1020 bytes)
in Imm to the current value of the SP (R7).
Load the word from the resulting address into
Rd.
Word 8
Action
0
S3C2410A