s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 54

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s3c2410a

Manufacturer Part Number
s3c2410a
Description
16/32-bit Risc Arm Microprocessor
Manufacturer
Samsung Semiconductor, Inc.
Datasheet

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PRODUCT OVERVIEW
1-24
Reset, Clock & Power (Continued)
EXTCLK
XTIpll
XTOpll
MPLLCAP
UPLLCAP
XTIrtc
XTOrtc
CLKOUT [1:0]
Signal
I/O
AO
AO
AI
AI
AI
AI
O
I
External clock source.
When OM [3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.
When OM [3:2] = 10b, EXTCLK is used for MPLL CLK source only.
When OM [3:2] = 01b, EXTCLK is used for UPLL CLK source only.
If it isn't used, it has to be High (3.3V).
Crystal Input for internal osc circuit.
When OM [3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source.
When OM [3:2] = 01b, XTIpll is used for MPLL CLK source only.
When OM [3:2] = 10b, XTIpll is used for UPLL CLK source only.
If it isn't used, XTIpll has to be High (3.3V).
Crystal Output for internal osc circuit.
When OM [3:2] = 00b, XTIpll is used for MPLL CLK source and UPLL CLK source.
When OM [3:2] = 01b, XTIpll is used for MPLL CLK source only.
When OM [3:2] = 10b, XTIpll is used for UPLL CLK source only.
If it isn't used, it has to be a floating pin.
Loop filter capacitor for main clock.
Loop filter capacitor for USB clock.
32.768 kHz crystal input for RTC. If it isn't used, it has to be in High (RTCVDD = 1.8V).
32.768 kHz crystal output for RTC. If it isn't used, it has to be Float.
Clock output signal. The CLKSEL of MISCCR register configures the clock output
mode among the MPLL CLK, UPLL CLK, FCLK, HCLK and PCLK.
Table 1-3. S3C2410A Signal Descriptions (Continued)
Description
S3C2410A

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