s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 116

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM INSTRUCTION SET
HALFWORD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The
instruction encoding is shown in Figure 3-16.
These instructions are used to load or store half-words of data and also load sign-extended bytes or half-words of
data. The memory address used in the transfer is calculated by adding an offset to or subtracting an offset from a
base register. The result of this calculation may be written back into the base register if auto-indexing is required.
3-34
31
Cond
28
27
Figure 3-16. Halfword and Signed Data Transfer with Register Offset
000
25
24
P U
23
22
0
[3:0] Offset Register
[6][5] S H
[15:12] Source/Destination Register
[19:16] Base Register
[20] Load/Store
0 = Store to memory
1 = Load from memory
[21] Write-back
0 = No write-back
1 = Write address into base
[23] Up/Down
0 = Down: subtract offset from base
1 = Up: add offset to base
[24] Pre/Post Indexing
0 = Post: add/subtract offset after transfer
1 = Pre: add/subtract offset bofore transfer
[31:28] Condition Field
21
W
0 0 = SWP instruction
0 1 = Unsigned halfword
1 1 = Signed byte
1 1 = Signed halfword
20
L
19
Rn
16
15
Rd
12
11
0000
8 7 6 5 4 3
1
S H 1
Rm
0
S3C2410A