s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 539

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM920T PROCESSOR
Register 1 bits 31:30 select the clocking mode of the ARM920T, as shown in Table 2-11.
FastBus mode
Reserved
Synchronous
Asynchronous
Register Bits
29:15
11:10
6:3
31
30
14
13
12
9
8
7
2
1
0
Clocking Mode
Name
RR bit
nF bit
iA bit
M bit
V bit
R bit
S bit
B bit
C bit
A bit
I bit
–
–
–
Asynchronous clock select
notFastBus select
Reserved
Round robin replacement
Base location of exception
registers
Instruction cache enable
Reserved
ROM protection
System protection
Big-endian/little-endian
Reserved
Data cache enable
Alignment fault enable
MMU enable
Table 2-10. Control Register 1-bit Functions
Table 2-11. Clocking Modes
Function
iA
0
1
0
1
See Table 2-11 on page 2-11.
See Table 2-11 on page 2-11.
Read = Unpredictable
Write = Should be zero
0 = Random replacement
1 = Round robin replacement
0 = Low addresses = 0x0000 0000
1 = High addresses = 0xFFFF 0000
0 = Instruction cache disabled
1 = Instruction cache enabled
Read = 00
Write = 00
This bit modifies the MMU protection system.
See Table 3-6 on page 3-20
This bit modifies the MMU protection system.
See Table 3-6 on page 3-20
0 = Little-endian operation
1 = Big-endian operation
Read = 1111
Write = 1111
0 = Data cache disabled
1 = Data cache enabled
Data address alignment fault checing.
0 = Fault checking disabled
1 = Fault checking enabled
0 = MMU disabled
1 = MMU enabled
Value
PROGRAMMER'S MODEL
nF
0
0
1
1
2-11