s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 459

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
FLOWCHARTS OF OPERATIONS IN EACH MODE
The following steps must be executed before any IIC Tx/Rx operations.
1) Write own slave address on IICADD register, if needed.
2) Set IICCON register.
3) Set IICSTAT to enable Serial Output
a) Enable interrupt
b) Define SCL period
Figure 20-6. Operations for Master/Transmitter Mode
Write new data transmitted
Master Tx mode has been
Write 0xF0 (M/T Start) to
The data of the IICDS is
The data of the IICDS is
Write slave address to
ACK period and then
interrupt is pending.
Clear pending bit to
shifted to SDA.
transmitted.
configured.
IICSTAT.
to IICDS.
resume.
START
IICDS.
Stop?
N
Y
Write 0xD0 (M/T Stop) to
condition takes effect.
Wait until the stop
Clear pending bit.
IICSTAT.
END
IIC-BUS INTERFACE
20-7