s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 181

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
NOTES:
1.
2.
INSTRUCTION CYCLE TIMES
All instructions in this format have an equivalent ARM instruction as shown in Table 3-1. The instruction cycle times
for the THUMB instruction are identical to that of the equivalent ARM instruction.
EXAMPLES
over
1001
1010
1011
1100
1101
L
While label specifies a full 9-bit two's complement address, this must always be halfword-aligned (ie with bit 0 set to 0)
since the assembler actually places label >> 1 in field SOffset8.
Cond = 1110 is undefined, and should not be used.
Cond = 1111 creates the SWI instruction: see .
BLS label
BGE label
BLT label
BGT label
BLE label
THUMB assembler
CMP R0, #45 ;
BGT over
Table 4-17. The Conditional Branch Instructions (Continued)
BLS label
BGE label
BLT label
BGT label
BLE label
ARM equivalent
Branch to over-if R0 > 45.
; Note that the THUMB opcode will contain
; the number of halfwords to offset.
; Must be halfword aligned.
Branch if C clear or Z set (unsigned lower or
same)
Branch if N set and V set, or N clear and V
clear (greater or equal)
Branch if N set and V clear, or N clear and V
set (less than)
Branch if Z clear, and either N set and V set
or N clear and V clear (greater than)
Branch if Z set, or N set and V clear, or N
clear and V set (less than or equal)
Action
THUMB INSTRUCTION SET
4-35