s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 582

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

CACHES, WRITE BUFFER
ARM920T PROCESSOR
INSTRUCTION CACHE REPLACEMENT ALGORITHM
The ICache and DCache replacement algorithm is selected by the RR bit in the CP15 control register (CP15 register
1, bit 14). Random replacement is selected at reset. Setting the RR bit to 1 selects round-robin replacement.
INSTRUCTION CACHE LOCKDOWN
Instructions can be locked into the ICache, causing the ICache to guarantee a hit, and providing optimum and
predictable execution time.
Instructions are locked into the ICache by first ensuring the code to be locked is not already in the cache. This is
tested by flushing either the whole ICache or specific lines. A short software routine can then be used to load the
instructions into the ICache. The software routine must either be non-cacheable, or already in the ICache, but not in
an ICache line which is about to be overwritten. The instructions to be loaded must be from a memory region which is
cacheable.
The software routine operates by writing to CP15 register 9 to force the replacement counter to a specific ICache line
and by using the prefetch ICache line operation available via CP15 register 7 to force the ICache to perform a lookup.
This will miss and a linefill will be performed loading the cache line into the entry specified by the replacement
counter. Once all the instructions have been loaded, they are then locked by writing to CP15 register 9 to set the
replacement counter base to be one higher than the number of locked cache lines.
See Data cache lockdown on page 4-9 for a more complete explanation of cache locking.
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