s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 90

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM INSTRUCTION SET
ASSEMBLER SYNTAX
Items in {} are optional. Items in <> must be present.
B{L}{cond} <expression>
{L}
{cond}
<expression>
Examples
here
3-8
BAL
B
CMP
BEQ
BL
ADDS
BLCC
Used to request the Branch with Link form of the instruction. If absent, R14 will not be
affected by the instruction.
A two-character mnemonic as shown in Table 3-2. If absent then AL (ALways) will be
used.
The destination. The assembler calculates the offset.
here
there
R1,#0
fred
sub+ROM
R1,#1
sub
; Assembles to 0xEAFFFFFE (note effect of PC offset).
; Always condition used as default.
; Compare R1 with zero and branch to fred
; if R1 was zero, otherwise continue.
; Continue to next instruction.
; Call subroutine at computed address.
; Add 1 to register 1, setting CPSR flags
; on the result then call subroutine if
; the C flag is clear, which will be the
; case unless R1 held 0xFFFFFFFF.
S3C2410A