s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 129

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
SINGLE DATA SWAP (SWP)
The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The
instruction encoding is shown in Figure 3-23.
The data swap instruction is used to swap a byte or word quantity between a register and external memory. This
instruction is implemented as a memory read followed by a memory write which are "locked" together (the processor
cannot be interrupted until both operations have completed, and the memory manager is warned to treat them as
inseparable). This class of instruction is particularly useful for implementing software semaphores.
The swap address is determined by the contents of the base register (Rn). The processor first reads the contents of
the swap address. Then it writes the contents of the source register (Rm) to the swap address, and stores the old
memory contents in the destination register (Rd). The same register may be specified as both the source and
destination.
The LOCK output goes HIGH for the duration of the read and write operations to signal to the external memory
manager that they are locked together, and should be allowed to complete without interruption. This is important in
multi-processor systems where the swap instruction is the only indivisible instruction which may be used to
implement semaphores; control of the memory must not be removed from a processor while it is performing a locked
operation.
BYTES AND WORDS
This instruction class may be used to swap a byte (B = 1) or a word (B = 0) between an ARM920T register and
memory. The SWP instruction is implemented as a LDR followed by a STR and the action of these is as described
in the section on single data transfers. In particular, the description of Big and Little Endian configuration applies to
the SWP instruction.
31
Cond
28
27
00010
23
22
B
21
00
Figure 3-23. Swap Instruction
20
[3:0] Source Register
[15:12] Destination Register
[19:16] Base Register
[22] Byte/Word Bit
0 = Swap word quantity
1 = Swap word quantity
[31:28] Condition Field
19
Rn
16
15
Rd
12
11
0000
8 7
1001
4 3
ARM INSTRUCTION SET
Rm
0
3-47