s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 143

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
5. Overflow in unsigned multiply accumulate with a 64-bit result
6. Overflow in signed multiply accumulate with a 64-bit result
PSEUDO-RANDOM BINARY SEQUENCE GENERATOR
It is often necessary to generate (pseudo-) random numbers and the most efficient algorithms are based on shift
generators with exclusive-OR feedback rather like a cyclic redundancy check generator. Unfortunately the sequence
of a 32-bit generator needs more than one feedback tap to be maximal length (i.e. 2^32-1 cycles before repetition),
so this example uses a 33-bit register with taps at bits 33 and 20. The basic algorithm is newbit:=bit 33 eor bit 20,
shift left the 33-bit number and put in newbit at the bottom; this operation is performed for all the newbits needed (i.e.
32 bits). The entire operation can be done in 5 S cycles:
MULTIPLICATION BY CONSTANT USING THE BARREL SHIFTER
Multiplication by 2^n (1,2,4,8,16,32..)
Multiplication by 2^n+1 (3,5,9,17..)
Multiplication by 2^n-1 (3,7,15..)
Overflow checking is not applicable to unsigned and signed multiplies with a 64-bit result, since overflow
does not occur in such calculations.
UMULL
ADDS
ADC
BCS
SMULL
ADDS
ADC
BVS
TST
MOVS
ADC
EOR
EOR
MOV
ADD
RSB
Rl,Rh,Rm,Rn
Rl,Rl,Ra1
Rh,Rh,Ra2
overflow
Rl,Rh,Rm,Rn
Rl,Rl,Ra1
Rh,Rh,Ra2
overflow
Rb,Rb,LSR#1
Rc,Ra,RRX
Rb,Rb,Rb
Rc,Rc,Ra,LSL#12
Ra,Rc,Rc,LSR#20
Ra, Rb, LSL #n
Ra,Ra,Ra,LSL #n
Ra,Ra,Ra,LSL #n
NOTE
; 3 to 6 cycles
; Lower accumulate
; Upper accumulate
; 1 cycle and 2 registers
; 3 to 6 cycles
; Lower accumulate
; Upper accumulate
; 1 cycle and 2 registers
; Enter with seed in Ra (32 bits),
; Rb (1 bit in Rb lsb), uses Rc.
; Top bit into carry
; 33 bit rotate right
; Carry into lsb of Rb
; (involved!)
; (similarly involved!) new seed in Ra, Rb as before
ARM INSTRUCTION SET
3-61