s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 159

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE
OPERATION
There are four sets of instructions in this group. The first three allow ADD, CMP and MOV operations to be performed
between Lo and Hi registers, or a pair of Hi registers. The fourth, BX, allows a Branch to be performed which may
also be used to switch processor state. The THUMB assembler syntax is shown in Table 4-6.
The action of H1= 0, H2 = 0 for Op = 00 (ADD), Op =01 (CMP) and Op = 10 (MOV) is undefined, and should not be
used.
Op
00
00
00
01
01
In this group only CMP (Op = 01) sets the CPSR condition codes.
15
0
H1
0
1
1
0
1
14
0
H2
1
0
1
1
0
13
0
ADD Rd, Hs
ADD Hd, Rs
ADD Hd, Hs
CMP Rd, Hs
CMP Hd, Rs
THUMB assembler
12
0
Table 4-6. Summary of Format 5 Instructions
11
0
10
0
[2:0] Destination Register
[5:3] Source Register
[6] Hi Operand Flag 2
[7] Hi Operand Flag 1
[9:8] Opcode
Figure 4-6. Format 5
9
Op
ADD Rd, Rd, Hs
ADD Hd, Hd, Rs
ADD Hd, Hd, Hs
CMP Rd, Hs
CMP Hd, Rs
ARM equivalent
8
NOTE
H1
7
H2
6
5
Add a register in the range 8-15 to a
register in the range 0-7.
Add a register in the range 0-7 to a
register in the range 8-15.
Add two registers in the range 8-15
Compare a register in the range 0-7
with a register in the range 8-15. Set
the condition code flags on the result.
Compare a register in the range 8-15
with a register in the range 0-7. Set the
condition code flags on the result.
Rs/Hs
3
THUMB INSTRUCTION SET
2
Action
Rd/Hd
0
4-13