s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 463

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
IIC-BUS INTERFACE SPECIAL REGISTERS
MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER
NOTES:
1. Interfacing with EEPROM, the ack generation may be disabled before reading the last data in order to generate the
2.
3. To adjust the setup time of IICSDA before IISSCL rising edge, IICDS has to be written before clearing the IIC interrupt
4.
5.
IICCON
Acknowledge
generation
Tx clock source
selection
Tx/Rx Interrupt
(note 5)
Interrupt pending
flag
Transmit clock
value
STOP condition in Rx mode.
pending bit.
Register
An IIC-bus interrupt occurs 1) when a 1-byte transmit or receive operation is completed, 2) when a general call or a
slave address match occurs, or 3) if bus arbitration fails.
IICCLK is determined by IICCON[6].
Tx clock can vary by SCL transition time.
When IICCON[6]=0, IICCON[3:0]=0x0 or 0x1 is not available.
If the IICON[5]=0, IICON[4] does not operate correctly.
So, It is recommended that you should set IICCON[5]=1, although you does not use the IIC interrupt.
(note 2), (note 3)
(note 4)
IICCON
(note 1)
0x54000000
Address
[3:0]
Bit
[7]
[6]
[5]
[4]
IIC-bus acknowledge enable bit.
0 = Disable,
In Tx mode, the IICSDA is free in the ack time.
In Rx mode, the IICSDA is L in the ack time.
Source clock of IIC-bus transmit clock prescaler selection bit.
0 = IICCLK = f
1 = IICCLK = f
IIC-Bus Tx/Rx interrupt enable/disable bit.
0 = Disable,
IIC-bus Tx/Rx interrupt pending flag. This bit cannot be written to
1. When this bit is read as 1, the IICSCL is tied to L and the IIC is
stopped. To resume the operation, clear this bit as 0.
0 = 1) No interrupt pending (when read).
1 = 1) Interrupt is pending (when read)
IIC-Bus transmit clock prescaler.
IIC-Bus transmit clock frequency is determined by this 4-bit
prescaler value, according to the following formula:
Tx clock = IICCLK/(IICCON[3:0]+1).
2) Clear pending condition &
2) N/A (when write)
Resume the operation (when write).
R/W
R/W
PCLK
PCLK
1 = Enable
1 = Enable
IIC-Bus control register
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Description
Description
IIC-BUS INTERFACE
Reset Value
Initial State
Undefined
0x0X
0
0
0
0
20-11