s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 170

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

THUMB INSTRUCTION SET
FORMAT 10: LOAD/STORE HALFWORD
OPERATION
These instructions transfer halfword values between a Lo register and memory. Addresses are pre-indexed, using a
6-bit immediate value. The THUMB assembler syntax is shown in Table 4-11.
NOTE:
4-24
L
0
1
#Imm is a full 6-bit address but must be halfword-aligned (ie with bit 0 set to 0) since the assembler places
#Imm >> 1 in the Offset5 field.
STRH Rd, [Rb, #Imm]
LDRH Rd, [Rb, #Imm]
15
0
THUMB assembler
14
1
13
0
12
0
Table 4-11. Halfword Data Transfer Instructions
11
L
STRH Rd, [Rb, #Imm]
LDRH Rd, [Rb, #Imm]
10
[2:0] Source/Destination Register
[5:3] Base Register
[10:6] Immediate Value
[11] Load/Store Flag
0 = Store to memory
1 = Load from memory
ARM equivalent
Figure 4-11. Format 10
Offset5
6
Add #Imm to base address in Rb and store
bits 0 - 15 of Rd at the resulting address.
Add #Imm to base address in Rb. Load bits
0-15 from the resulting address into Rd and
set bits 16-31 to zero.
5
Rb
3
Action
2
Rd
0
S3C2410A