s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 183

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
FORMAT 18: UNCONDITIONAL BRANCH
OPERATION
This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below. The branch offset
must take account of the prefetch operation, which causes the PC to be 1 word (4 bytes) ahead of the current
instruction.
NOTE:
EXAMPLES
here
jimmy
B label
THUMB assembler
The address specified by label is a full 12-bit two's complement address,
but must always be halfword aligned (ie bit 0 set to 0), since the assembler places label >> 1 in the Offset11 field.
15
1
B here
B jimmy
14
1
13
1
12
0
BAL label (halfword offset)
Table 4-19. Summary of Branch Instruction
11
0
ARM equivalent
10
[10:0] Immediate Value
Figure 4-19. Format 18
; Branch onto itself. Assembles to 0xE7FE.
; (Note effect of PC offset).
; Branch to 'jimmy'.
; Note that the THUMB opcode will contain the number of
; halfwords to offset.
; Must be halfword aligned.
Branch PC relative +/- Offset11 << 1, where label is
PC +/- 2048 bytes.
Offset11
Action
THUMB INSTRUCTION SET
0
4-37