s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 137

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
ASSEMBLER SYNTAX
<LDC|STC>{cond}{L} p#,cd,<Address>
LDC
STC
{L}
{cond}
p#
cd
<Address>
1
2
3
EXAMPLES
If Rn is R15, the assembler will subtract 8 from the offset value to allow for ARM920T pipelining.
Although the address offset is expressed in bytes, the instruction offset field is in words. The assembler will
adjust the offset appropriately.
LDC
STCEQL
Load from memory to coprocessor
Store from coprocessor to memory
When present perform long transfer (N = 1), otherwise perform short transfer (N = 0)
Two character condition mnemonic. See Table 3-2..
The unique number of the required coprocessor
An expression evaluating to a valid coprocessor register number that is placed in the
CRd field
can be:
An expression which generates an address:
The assembler will attempt to generate an instruction using the PC as a base and a
corrected immediate offset to address the location given by evaluating the expression.
This will be a PC relative, pre-indexed address. If the address is out of range, an error
will be generated
A pre-indexed addressing specification:
[Rn]
[Rn,<#expression>]{!}
A post-indexed addressing specification:
[Rn],<#expression
{!}
Rn
p1,c2,table
p2,c3,[R5,#24]!
NOTE
NOTE
; Load c2 of coproc 1 from address
; table, using a PC relative address.
; Conditionally store c3 of coproc 2
; into an address 24 bytes up from R5,
; write this address back to R5, and use
; long transfer option (probably to store multiple words).
offset of zero
offset of <expression> bytes
offset of <expression> bytes
write back the base register (set the W bit) if! is present
is an expression evaluating to a valid
ARM920T register number.
ARM INSTRUCTION SET
3-55