s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 569

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

ARM920T PROCESSOR
SUB-PAGES
Access permissions can be defined for sub pages of small and large pages. If, during a page walk, a small or large
page has a non-identical sub page permission, only the sub page being accessed is written into the TLB. For
example, a 16KB (large page) sub page entry will be written into the TLB if the sub page permission differs and a
64KB entry will be put in the TLB if the sub page permissions are identical.
When sub page permissions are used and the page entry then needs invalidating, all four sub pages must be
invalidated separately.
MMU FAULTS AND CPU ABORTS
The MMU generates an abort on the following types of faults:
In addition, an external abort may be raised by the external system as a result of certain types of external data
access.
Alignment fault checking is enabled by the A-bit in CP15 register 1. Alignment fault checking is not affected by
whether or not the MMU is enabled. Translation, domain and permission faults are only generated when the MMU is
enabled.
The access control mechanisms of the MMU detect the conditions that produce these faults. If a fault is detected as
the result of a memory access, the MMU will abort the access and signal the fault condition to the CPU core. The
MMU retains status and address information about faults generated by the data accesses in the fault status register
and fault address register (see section Fault address and fault status registers on page 3-18). The MMU does not
retain status about faults generated by instruction fetches.
An access violation for a given memory access inhibits any corresponding external access, with an abort returned to
the CPU core.
alignment faults (data accesses only)
translation faults
domain faults
permission faults.
MMU
3-17