s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 93

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
CPSR FLAGS
The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST,
TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to
produce the result. If the S bit is set (and Rd is not R15, see below) the V flag in the CPSR will be unaffected, the C
flag will be set to the carry out from the barrel shifter (or preserved when the shift operation is LSL #0), the Z flag will
be set if and only if the result is all zeros, and the N flag will be set to the logical value of bit 31 of the result.
The arithmetic operations (SUB, RSB, ADD, ADC, SBC, RSC, CMP, CMN) treat each operand as a 32 bit integer
(either unsigned or 2's complement signed, the two are equivalent). If the S bit is set (and Rd is not R15) the V flag in
the CPSR will be set if an overflow occurs into bit 31 of the result; this may be ignored if the operands were
considered unsigned, but warns of a possible error if the operands were 2's complement signed. The C flag will be
set to the carry out of bit 31 of the ALU, the Z flag will be set if and only if the result was zero, and the N flag will be
set to the value of bit 31 of the result (indicating a negative result if the operands are considered to be 2's
complement signed).
Assembler Mnemonic
WUB
MOV
EOR
CMP
CMN
ORR
MVN
AND
RSB
ADD
ADC
SBC
RSC
TEQ
TST
BIC
Table 3-3. ARM Data Processing Instructions
OP Code
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Operand1 AND operand2
Operand1 EOR operand2
Operand1 - operand2
Operand2 operand1
Operand1 + operand2
Operand1 + operand2 + carry
Operand1 - operand2 + carry - 1
Operand2 - operand1 + carry - 1
As AND, but result is not written
As EOR, but result is not written
As SUB, but result is not written
As ADD, but result is not written
Operand1 OR operand2
Operand2 (operand1 is ignored)
Operand1 AND NOT operand2 (Bit clear)
NOT operand2 (operand1 is ignored)
Action
ARM INSTRUCTION SET
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