s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 127

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
ASSEMBLER SYNTAX
<LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^}
where:
{cond}
Rn
<Rlist>
{!}
{^}
Addressing Mode Names
There are different assembler mnemonics for each of the addressing modes, depending on whether the instruction is
being used to support stacks or for other purposes. The equivalence between the names and the values of the bits in
the instruction are shown in the following table 3-6.
FD, ED, FA, EA define pre/post indexing and the up/down bit by reference to the form of stack required. The F and E
refer to a "full" or "empty" stack, i.e. whether a pre-index has to be done (full) before storing to the stack. The A and
D refer to whether the stack is ascending or descending. If ascending, a STM will go up and LDM down, if
descending, vice-versa.
IA, IB, DA, DB allow control when LDM/STM are not being used for stacks and simply mean Increment After,
Increment Before, Decrement After, Decrement Before.
Pre-Increment Load
Post-Increment Load
Pre-Decrement Load
Post-Decrement Load
Pre-Increment Store
Post-Increment Store
Pre-Decrement Store
Post-Decrement Store
Name
Two character condition mnemonic. See Table 3-2.
An expression evaluating to a valid register number
A list of registers and register ranges enclosed in {} (e.g. {R0,R2-R7,R10}).
If present requests write-back (W = 1), otherwise W = 0.
If present set S bit to load the CPSR along with the PC, or force transfer of user bank
when in privileged mode.
Table 3-6. Addressing Mode Names
LDMED
LDMFD
LDMEA
LDMFA
STMFA
STMEA
STMFD
STMED
Stack
LDMDB
LDMDA
STMDB
STMDA
LDMIB
LDMIA
STMIB
STMIA
Other
L bit
1
1
1
1
0
0
0
0
P bit
ARM INSTRUCTION SET
1
0
1
0
1
0
1
0
U bit
1
1
0
0
1
1
0
0
3-45