s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 337

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
END POINT0 CONTROL STATUS REGISTER (EP0_CSR) (Continued)
IN_PKT_RDY
OUT_PKT_RDY
EP0_CSR
Bit
[1]
[0]
MCU
SET
R
CLEAR
USB
SET
Set by the MCU after writing a packet of data
into EP0 FIFO. The USB clears this bit once
the packet has been successfully sent to the
host. An interrupt is generated when the USB
clears this bit, so as the MCU to load the next
packet. For a zero length data phase, the
MCU sets DATA_END at the same time.
Set by the USB once a valid token is written
to the FIFO. An interrupt is generated when
the USB sets this bit. The MCU clears this bit
by writing a "1" to the
SERVICED_OUT_PKT_RDY bit.
Description
Initial State
USB DEVICE
0
0
13-13