s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 166

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

THUMB INSTRUCTION SET
FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALFWORD
OPERATION
These instructions load optionally sign-extended bytes or halfwords, and store halfwords. The THUMB assembler
syntax is shown below.
4-20
L
0
0
1
1
15
0
B
0
1
0
1
14
1
STRH Rd, [Rb, Ro]
LDRH Rd, [Rb, Ro]
LDSB Rd, [Rb, Ro]
LDSH Rd, [Rb, Ro]
THUMB assembler
13
0
12
1
Table 4-9. Summary of format 8 instructions
11
H
10
S
[2:0] Destination Register
[5:3] Base Register
[8:6] Offset Register
[10] Sign-Extended Flag
0 = Operand not sing-extended
1 = Operand sing-extended
[11] H Flag
STRH Rd, [Rb, Ro]
LDRH Rd, [Rb, Ro]
LDRSB Rd, [Rb, Ro]
LDRSH Rd, [Rb, Ro]
Figure 4-9. Format 8
9
1
ARM equivalent
8
Ro
6
Store halfword:
Add Ro to base address in Rb. Store bits
0-15 of Rd at the resulting address.
Load halfword:
Add Ro to base address in Rb. Load bits
0-15 of Rd from the resulting address, and
set bits 16-31 of Rd to 0.
Load sign-extended byte:
Add Ro to base address in Rb. Load bits
0-7 of Rd from the resulting address, and
set bits 8-31 of Rd to bit 7.
Load sign-extended halfword:
Add Ro to base address in Rb. Load bits
0-15 of Rd from the resulting address, and
set bits 16-31 of Rd to bit 15.
5
Rb
3
Action
2
Rd
0
S3C2410A