s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 244

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

DMA
Demand/Handshake Mode Comparison
Demand and Handshake modes are related to the protocol between XnXDREQ and XnXDACK. Figure 8-2 shows the
differences between the two modes.
At the end of one transfer (Single/Burst transfer), DMA checks the state of double-synched XnXDREQ.
Demand Mode
— If XnXDREQ remains asserted, the next transfer starts immediately. Otherwise it waits for XnXDREQ to be
Handshake Mode
— If XnXDREQ is deasserted, DMA deasserts XnXDACK in 2cycles. Otherwise it waits until XnXDREQ is
8-4
XnXDACK
asserted.
deasserted.
Handshake Mode
Demand Mode
XnXDACK
XnXDREQ
XnXDREQ
XSCLK
XnXDREQ has to be asserted (low) only after the deassertion (high) of XnXDACK.
Double synch
Figure 8-2. Demand/Handshake Mode Comparison
Acquisiton
1st Transfer
BUS
Read
Read
2cycles
Transfer
Actual
Write
Write
CAUTION
2cycles
2nd Transfer
Double synch
Read
Write
2cycles
S3C2410A