s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 274

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

I/O PORTS
MISCELLANEOUS CONTROL REGISTER (MISCCR)
Pads related USB are controlled by this register for USB host, or for USB device.
NOTE:
9-20
USBSUSPND1
USBSUSPND0
nEN_SCLK1
nEN_SCLK0
nEN_SCKE
nRSTCON
SPUCR_H
SPUCR_L
CLKSEL1
CLKSEL0
USBPAD
Register
Reserved
Reserved
Reserved
Reserved
Reserved
MISCCR
MISCCR
CLKOUT is prepared only for monitoring an internal clock situation (On/Off status or frequency).
0x56000080
Address
[21:20]
[15:14]
[10:8]
[6:4]
[19]
[18]
[17]
[16]
[13]
[12]
[11]
Bit
[7]
[3]
[2]
[1]
[0]
Reserved to 00b
0: SCKE = Normal
Used to protect SDRAM during the Power_OFF moe.
0: SCLK1 = SCLK
Used to protect SDRAM during the Power_OFF moe.
0: SCLK0 = SCLK
Used to protect SDRAM during the Power_OFF moe.
nRSTOUT software control (SW_RESET)
0: nRSTOUT = 0, 1: nRSTOUT = 1.
Reserved to 00b
[13] USB Port 1 mode
0 = Normal
[12] USB Port 0 mode
0 = Normal
Reserved to 0b
CLKOUT1 output singnal source
000 = MPLL CLK
011 = HCLK
11x = Reserved
0
CLKOUT0 output singnal source
000 = MPLL CLK
011 = HCLK
11x = Reserved
0 = Use pads related USB for USB device
1 = Use pads related USB for USB host
Reserved to 0b.
DATA[15:0] port pull-up resister
0 = Enabled
DATA[31:16] port pull-up resister
0 = Enabled
R/W
R/W
Miscellaneous control register
1= Suspend
1= Suspend
1 = Disabled
1 = Disabled
001 = UPLL CLK
001 = UPLL CLK
100 = PCLK
100 = PCLK
1: SCKE = L level
1: SCLK1 = L level
1: SCLK0 = L level
Description
Description
010 = FCLK
010 = FCLK
101 = DCLK1
101 = DCLK0
Reset Value
0x10330
S3C2410A