s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 574

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

MMU
ALIGNMENT FAULT
If alignment fault is enabled (A-Bit in CP15 register 1 set), the MMU will generate an alignment fault on any data word
access the address of which is not word aligned, or on any halfword access the address of which is not halfword
aligned, irrespective of whether the MMU is enabled or not. An alignment fault will not be generated on any
instruction fetch, nor on any byte access.
TRANSLATION FAULT
There are two types of translation fault, section and page:
Section
Page
DOMAIN FAULT
There are two types of domain fault, section and page. In both cases the level one descriptor holds the 4-bit domain
field which selects one of the 16 2-bit domains in the domain access control register. The two bits of the specified
domain are then checked for access permissions as detailed in Table 3-6 on page 3-20. In the case of a section, the
domain is checked once the level one descriptor is returned and in the case of a page, the domain is checked once
the level one descriptor is returned.
If the specified access is either no access (00) or reserved (10) then either a section domain fault or page domain
fault occurs.
3-22
If the access generates an alignment fault, the access sequence will abort without reference to further
permission checks.
A section translation fault is generated if the level one descriptor is marked as invalid.
This happens if bits[1:0] of the descriptor are both 0.
A page translation fault is generated if the level one descriptor is marked as invalid. This
happens if bits[1:0] of the descriptor are both 0.
NOTE
ARM920T PROCESSOR