s3c2410a Samsung Semiconductor, Inc., s3c2410a Datasheet - Page 457

• Manufacturer Part Number: s3c2410a
• Description: 16/32-bit Risc Arm Microprocessor
• Manufacturer: Samsung Semiconductor, Inc.

S3C2410A
ACK SIGNAL TRANSMISSION
To complete a one-byte transfer operation, the receiver should send an ACK bit to the transmitter. The ACK pulse
should occur at the ninth clock of the SCL line. Eight clocks are required for the one-byte data transfer. The master
should generate the clock pulse required to transmit the ACK bit.
The transmitter should release the SDA line by making the SDA line High when the ACK clock pulse is received. The
receiver should also drive the SDA line Low during the ACK clock pulse so that the SDA keeps Low during the High
period of the ninth SCL pulse.
The ACK bit transmit function can be enabled or disabled by software (IICSTAT). However, the ACK pulse on the
ninth clock of SCL is required to complete the one-byte data transfer operation.
SDA
SCL
Data Output by
Transmitter
Data Output by
Receiver
SCL from
Master
S
MSB
1
Condition
Start
S
2
Byte Complete, Interrupt
within Receiver
Figure 20-4. Data Transfer on the IIC-Bus
Figure 20-5. Acknowledge on the IIC-Bus
7
Acknowledgement
Signal from Receiver
1
8
ACK
9
2
1
receiver and/or transmitter
2
Clock Line Held Low by
7
Clock Pulse for Acknowledgment
8
Acknowledgement
Signal from Receiver
Clock to Output
9
IIC-BUS INTERFACE
9
20-5