MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 120

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Clock Generator Module (CGM)
Advance Information
120
is the time taken to return from 900 kHz to 1 MHz 5 kHz. Five kHz = 5%
of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are as follows:
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
•
•
Acquisition time, t
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance,
Acquisition time is based on an initial frequency error, [(f
f
control mode (see
Bandwidth
becomes set in the PLL bandwidth control register (PBWC).
Lock time, t
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance,
time is based on an initial frequency error, [(f
more than 100%. In automatic bandwidth control mode, lock time
expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). (See
PLL Bandwidth
ORIG
)/f
Clock Generator Module (CGM)
DES
], of not more than 100%. In automatic bandwidth
LOCK
Modes), acquisition time expires when the ACQ bit
, is the time the PLL takes to reduce the error
Modes.)
ACQ
8.4.2.3 Manual and Automatic PLL
, is the time the PLL takes to reduce the error
8.4.2.3 Manual and Automatic
MC68HC708AS48
DES
– f
ORIG
)/f
MOTOROLA
DES
LOCK
—
DES
], of not
Rev. 4.0
. Lock
TRK
–
.