MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 298

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Serial Peripheral Interface (SPI)
18.7.2 Mode Fault Error
Advance Information
298
READ SPSCR
SPI RECEIVE
READ SPDR
COMPLETE
Figure 18-9. Clearing SPRF When OVRF Interrupt Is Not Enabled
OVRF
SPRF
1
2
3
4
5
6
7
BYTE 1
BYTE 2 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
BYTE 1 SETS SPRF BIT.
CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
1
For the MODF flag (in SPSCR) to be set, the mode fault error enable bit
(MODFEN in SPSCR) must be set. Clearing the MODFEN bit does not
clear the MODF flag but does prevent MODF from being set again after
MODF is cleared.
MODF generates a receiver/error CPU interrupt request if the error
interrupt enable bit (ERRIE in SPSCR) is also set. The SPRF, MODF,
and OVRF interrupts share the same CPU interrupt vector. MODF and
OVRF can generate a receiver/error CPU interrupt request. (See
18-10.) It is not possible to enable only MODF or OVRF to generate a
receiver/error CPU interrupt request. However, leaving MODFEN low
prevents MODF from being set.
2
3
Serial Peripheral Interface (SPI)
4
BYTE 2
5
BYTE 3
6
7
10
11
12
13
14
8
9
8
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
BYTE 4 SETS SPRF BIT.
CPU READS SPSCR.
CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
9
BYTE 4
10
11
MC68HC708AS48
12
13
14
MOTOROLA
—
Figure
Rev. 4.0