MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 227

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
16.8 I/O Signals
Port D shares one of its pins with the TIM. Port E shares two of its pins
with the TIM and port F shares four of its pins with the TIM.
PTD6/ATD14/TCLK is an external clock input to the TIM prescaler. The
six TIM channel I/O pins are PTE2/TCH0, PTE3/TCH1, PTF0/TCH2,
PTF1/TCH3, PTF2/TCH4, and PTF3/TCH5.
16.8.1 TIM Clock Pin (PTD6/ATD14/TCLK)
PTD6/ATD14/TCLK is an external clock input that can be the clock
source for the TIM counter instead of the prescaled internal bus clock.
Select the PTD6/ATD14/TCLK input by writing logic 1s to the three
prescaler select bits, PS[2:0]. (See
Register.) The minimum TCLK pulse width, TCLK
The maximum TCLK frequency is the least: 4 MHz or bus frequency 2.
PTD6/ATD14/TCLK is available as a general-purpose I/O pin or ADC
channel when not used as the TIM clock input. When the
PTD6/ATD14/TCLK pin is the TIM clock input, it is an input regardless of
the state of the DDRD6 bit in data direction register D.
16.8.2 TIM Channel I/O Pins (PTF3/TCH5–PTF0/TCH2, PTE3/TCH1–PTE2/TCH0)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE2/TCH0, PTE6/TCH2, and
PTF2/TCH4 can be configured as buffered output compare or buffered
PWM pins.
MC68HC708AS48
Rev. 4.0
MOTOROLA
16.9.1 TIM Status and Control
1
------------------------------------ -
+
bus frequency
Timer Interface (TIM)
Timer Interface (TIM)
I/O Signals
or TCLK
, is:
HMIN
LMIN
t
SU
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227

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