MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 206

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Input/Output (I/O) Ports
15.8.2 Data Direction Register F
Advance Information
206
NOTE:
NOTE:
Address:
determine whether reading port F returns the states of the latches or the
states of the pins. (See
Data direction register F determines whether each port F pin is an input
or an output. Writing a logic 1 to a DDRF bit enables the output buffer for
the corresponding port F pin; a logic 0 disables the output buffer.
DDRF[4:0] — Data Direction Register F Bits
DDRF4 is available only in the 64-pin QFP package.
Avoid glitches on port F pins by writing to the port F data register before
changing data direction register F bits from 0 to 1.
Figure 15-19
Reset:
Read:
Write:
These read/write bits control port F data direction. Reset clears
DDRF[4:0], configuring all port F pins as inputs.
1 = Corresponding port F pin configured as output
0 = Corresponding port F pin configured as input
$000D
Bit 7
Figure 15-18. Data Direction Register F (DDRF)
R
R
0
0
shows the port F I/O logic.
Input/Output (I/O) Ports
= Reserved
R
6
0
0
Table
R
5
0
0
15-6.)
DDRF4
4
0
DDRF3
3
0
MC68HC708AS48
DDRF2
2
0
DDRF1
1
0
MOTOROLA
—
Rev. 4.0
DDRF0
Bit 0
0