MC68HC708AS48

Manufacturer Part NumberMC68HC708AS48
DescriptionAdvance Information
ManufacturerFREESCALE [Freescale Semiconductor, Inc]
MC68HC708AS48 datasheet
 


1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
Page 341
342
Page 342
343
Page 343
344
Page 344
345
Page 345
346
Page 346
347
Page 347
348
Page 348
349
Page 349
350
Page 350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
Page 346/396

Download datasheet (4Mb)Embed
PrevNext
Byte Data Link Controller–Digital (BDLC–D)
Idle
An idle is defined as a passive period greater than 300 s in length.
20.5.4 J1850 VPW Valid/Invalid Bits and Symbols
The timing tolerances for receiving data bits and symbols from the
J1850 bus have been defined to allow for variations in oscillator
frequencies. In many cases, the maximum time allowed to define a data
bit or symbol is equal to the minimum time allowed to define another data
bit or symbol.
Since the minimum resolution of the BDLC for determining what symbol
is being received is equal to a single period of the MUX interface clock
(t
BDLC
concurrences equals one cycle of t
This one clock resolution allows the BDLC to differentiate properly
between the different bits and symbols. This is done without reducing the
valid window for receiving bits and symbols from transmitters onto the
J1850 bus, which has varying oscillator frequencies.
In Huntsinger’s variable pulse width (VPW) modulation bit encoding, the
tolerances for both the passive and active data bits received and the
symbols received are defined with no gaps between definitions. For
example, the maximum length of a passive logic 0 is equal to the
minimum length of a passive logic 1, and the maximum length of an
active logic 0 is equal to the minimum length of a valid SOF symbol.
Invalid Passive Bit
See
beginning the next data bit or symbol occurs between the
active-to-passive transition beginning the current data bit (or symbol)
and a, the current bit would be invalid.
Advance Information
346
), an apparent separation in these maximum time/minimum time
Figure
20-8(1). If the passive-to-active received transition
Byte Data Link Controller–Digital (BDLC–D)
.
BDLC
MC68HC708AS48
MOTOROLA
Rev. 4.0