MC68HC708AS48

Manufacturer Part NumberMC68HC708AS48
DescriptionAdvance Information
ManufacturerFREESCALE [Freescale Semiconductor, Inc]
MC68HC708AS48 datasheet
 
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Page 181/396

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14.5
Pin
IRQ/VPP
A logic 0 on the IRQ/V
latch. A vector fetch, software clear, or reset clears the IRQ latch.
If the MODE bit is set, the IRQ/V
low-level sensitive. With MODE set, both of the following actions must
occur to clear the IRQ latch:
The vector fetch or software clear and the return of the IRQ/V
logic 1 can occur in any order. The interrupt request remains pending as
long as the IRQ/V
MODE control bit, thereby clearing the interrupt even if the pin stays low.
If the MODE bit is clear, the IRQ/V
With MODE clear, a vector fetch or software clear immediately clears the
IRQ latch.
MC68HC708AS48
Rev. 4.0
MOTOROLA
pin can latch an interrupt request into the IRQ
PP
PP
Vector fetch or software clear — A vector fetch generates an
interrupt acknowledge signal to clear the latch. Software may
generate the interrupt acknowledge signal by writing a logic 1 to
the ACK bit in the interrupt status and control register (ISCR). The
ACK bit is useful in applications that poll the IRQ/V
require software to clear the IRQ latch. Writing to the ACK bit can
also prevent spurious interrupts due to noise. Setting ACK does
not affect subsequent transitions on the IRQ/V
edge on IRQ/V
that occurs after writing to the ACK bit latches
PP
another interrupt request. If the IRQ mask bit, IMASK, is clear, the
CPU loads the program counter with the vector address at
locations $FFFA and $FFFB.
Return of the IRQ/V
pin to logic 1 — As long as the IRQ/V
PP
is at logic 0, the IRQ latch remains set.
pin is at logic 0. A reset will clear the latch and the
PP
External Interrupt
External Interrupt
IRQ/VPP Pin
pin is both falling-edge sensitive and
pin and
PP
pin. A falling
PP
pin is falling-edge sensitive only.
PP
Advance Information
pin
PP
pin to
PP
181