MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 114

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
Clock Generator Module (CGM)
8.6.2 PLL Bandwidth Control Register
The PLL bandwidth control register:
In manual operation, forces the PLL into acquisition or tracking mode
Address:
Read:
Write:
Reset:
AUTO — Automatic Bandwidth Control Bit
This read/write bit selects automatic or manual bandwidth control.
When initializing the PLL for manual operation (AUTO = 0), clear the
ACQ bit before turning on the PLL. Reset clears the AUTO bit.
LOCK — Lock Indicator Bit
When the AUTO bit is set, LOCK is a read-only bit that becomes set
when the VCO clock, CGMVCLK, is locked (running at the
programmed frequency). When the AUTO bit is clear, LOCK reads as
logic 0 and has no meaning. Reset clears the LOCK bit.
Advance Information
114
Selects automatic or manual (software-controlled) bandwidth
control mode
Indicates when the PLL is locked
In automatic bandwidth control mode, indicates when the PLL is in
acquisition or tracking mode
$001D
Bit 7
6
5
4
LOCK
AUTO
ACQ
XLD
R
0
0
0
0
R
= Reserved
Figure 8-6. PLL Bandwidth Control Register (PBWC)
1 = Automatic bandwidth control
0 = Manual bandwidth control
1 = VCO frequency correct or locked
0 = VCO frequency incorrect or unlocked
Clock Generator Module (CGM)
3
2
1
Bit 0
0
0
0
0
R
R
R
R
0
0
0
0
MC68HC708AS48
Rev. 4.0
MOTOROLA

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