MC68HC708AS48

Manufacturer Part NumberMC68HC708AS48
DescriptionAdvance Information
ManufacturerFREESCALE [Freescale Semiconductor, Inc]
MC68HC708AS48 datasheet
 
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Page 203/396

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TxD — SCI Transmit Data Output
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. (See
17.9.1 SCI Control Register
NOTE:
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See
15.7.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
DDRE[7:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE[7:0], configuring all port E pins as inputs.
NOTE:
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 15-16
MC68HC708AS48
Rev. 4.0
MOTOROLA
$000C
Bit 7
6
5
DDRE7
DDRE6
DDRE5
DDRE4
0
0
0
Figure 15-15. Data Direction Register E (DDRE)
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
shows the port E I/O logic.
Input/Output (I/O) Ports
Input/Output (I/O) Ports
1.)
Table
15-5.)
4
3
2
1
DDRE3
DDRE2
DDRE1
0
0
0
0
Advance Information
Port E
Bit 0
DDRE0
0
203