MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 203

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

15.7.2 Data Direction Register E
MC68HC708AS48
MOTOROLA
NOTE:
NOTE:
—
Rev. 4.0
Address:
TxD — SCI Transmit Data Output
Data direction register E (DDRE) does not affect the data direction of
port E pins that are being used by the SCI module. However, the DDRE
bits always determine whether reading port E returns the states of the
latches or the states of the pins. (See
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
DDRE[7:0] — Data Direction Register E Bits
Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
Figure 15-16
Reset:
Read:
Write:
The PTE0/TxD pin is the transmit data output for the SCI module.
When the enable SCI bit, ENSCI, is clear, the SCI module is disabled,
and the PTE0/TxD pin is available for general-purpose I/O. (See
17.9.1 SCI Control Register
These read/write bits control port E data direction. Reset clears
DDRE[7:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
DDRE7
$000C
Bit 7
Figure 15-15. Data Direction Register E (DDRE)
0
shows the port E I/O logic.
Input/Output (I/O) Ports
DDRE6
6
0
DDRE5
5
0
DDRE4
1.)
4
0
Table
DDRE3
3
0
15-5.)
DDRE2
2
0
Input/Output (I/O) Ports
Advance Information
DDRE1
1
0
DDRE0
Bit 0
Port E
0
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