MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 199

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MC68HC708AS48

Manufacturer Part Number
MC68HC708AS48
Description
Advance Information
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet
15.6.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer
for the corresponding port D pin; a logic 0 disables the output buffer.
Address:
Read:
Write:
Reset:
DDRD[7:3, 1:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:3, 1:0], configuring all port D pins as inputs.
NOTE:
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
NOTE:
DDRD7 is available only in the 64-pin QFP package.
Figure 15-13
MC68HC708AS48
Rev. 4.0
MOTOROLA
$0007
Bit 7
6
5
DDRD7
DDRD6
DDRD5
DDRD4
0
0
0
R
= Reserved
Figure 15-12. Data Direction Register D (DDRD)
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
shows the port D I/O logic PTD[7:3, 1:0].
Input/Output (I/O) Ports
Input/Output (I/O) Ports
4
3
2
1
0
DDRD3
DDRD1
R
0
0
0
0
Advance Information
Port D
Bit 0
DDRD0
0
199

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