MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 224

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Timer Interface (TIM)
Advance Information
224
NOTE:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable 0%
duty cycle generation and removes the ability of the channel to
self-correct in the event of software error or noise. Toggling on output
compare can also cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Setting MS0B links channels 0 and 1 and configures them for buffered
PWM operation. The TIM channel 0 registers (TCH0H–TCH0L) initially
control the buffered PWM output. TIM status control register 0 (TSCR0)
controls and monitors the PWM signal from the linked channels. MS0B
takes priority over MS0A.
Setting MS2B links channels 2 and 3 and configures them for buffered
PWM operation. The TIM channel 2 registers (TCH2H–TCH2L) initially
control the PWM output. TIM status control register 2 (TSCR2) controls
and monitors the PWM signal from the linked channels. MS2B takes
priority over MS2A.
Setting MS4B links channels 4 and 5 and configures them for buffered
PWM operation. The TIM channel 4 registers (TCH4H–TCH4L) initially
control the PWM output. TIM status control register 4 (TSCR4) controls
and monitors the PWM signal from the linked channels. MS4B takes
priority over MS4A.
4. In TIM channel x status and control register (TSCx):
5. In the TIM status control register (TSC), clear the TIM stop bit,
a. Write 0:1 (for unbuffered output compare or PWM signals) or
b. Write 1 to the toggle-on-overflow bit, TOVx.
c. Write 1:0 (to clear output on compare) or 1:1 (to set output on
TSTOP.
1:0 (for buffered output compare or PWM signals) to the mode
select bits, MSxB–MSxA. (See
compare) to the edge/level select bits, ELSxB–ELSxA. The
output action on compare must force the output to the
complement of the pulse width level. (See
Timer Interface (TIM)
Table
MC68HC708AS48
16-2.)
Table
16-2.)
MOTOROLA
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Rev. 4.0