MC68HC708AS48

Manufacturer Part NumberMC68HC708AS48
DescriptionAdvance Information
ManufacturerFREESCALE [Freescale Semiconductor, Inc]
MC68HC708AS48 datasheet
 


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Page 352/396

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Byte Data Link Controller–Digital (BDLC–D)
During arbitration, or even throughout the transmitting message, when
an opposite bit is detected, transmission is stopped immediately unless
it occurs on the 8th bit of a byte. In this case, the BDLC automatically will
append up to two extra logic 1 bits and then stop transmitting. These two
extra bits will be arbitrated normally and thus will not interfere with
another message. The second logic 1 bit will not be sent if the first loses
arbitration. If the BDLC has lost arbitration to another valid message,
then the two extra logic 1s will not corrupt the current message.
However, if the BDLC has lost arbitration due to noise on the bus, then
the two extra logic 1s will ensure that the current message will be
detected and ignored as a noise-corrupted message.
20.6 BDLC Protocol Handler
The protocol handler is responsible for framing, arbitration, CRC
generation/checking, and error detection. The protocol handler
conforms to SAE J1850 Class B Data Communications Network
Interface .
NOTE:
Motorola assumes that the reader is familiar with the J1850 specification
before reading this protocol handler description.
Advance Information
352
TO CPU
CPU INTERFACE
PROTOCOL HANDLER
MUX INTERFACE
PHYSICAL INTERFACE
TO J1850 BUS
Figure 20-13. BDLC Block Diagram
Byte Data Link Controller–Digital (BDLC–D)
BDLC
MC68HC708AS48
Rev. 4.0
MOTOROLA