MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 141

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

9.7 Low-Power Modes
9.7.1 Wait Mode
MC68HC708AS48
MOTOROLA
—
Rev. 4.0
Executing the WAIT or STOP instruction puts the MCU in a low-power
mode for standby situations. The SIM holds the CPU in a non-clocked
state. The operation of each of these modes is described below. Both
STOP and WAIT clear the interrupt mask (I) in the condition code
register, allowing interrupts to occur.
In wait mode, the CPU clocks are inactive while one set of peripheral
clocks continues to run.
entry.
A module that is active during wait mode can wake up the CPU with an
interrupt if the interrupt is enabled. Stacking for the interrupt begins one
cycle after the WAIT instruction during which the interrupt occurred.
Refer to the wait mode subsection of each module to see if the module
is active or inactive in wait mode. Some modules can be programmed to
be active in wait mode.
Wait mode also can be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the SIM
break status register (SBSR). If the COP disable bit, COPD, in the
configuration (CONFIG, $001F) register is logic 0, then the computer
operating properly module (COP) is enabled and remains active in wait
mode.
R/W
IAB
IDB
NOTE: Previous data can be operand data or the WAIT opcode, depending on the last instruction.
System Integration Module (SIM)
WAIT ADDR
PREVIOUS DATA
Figure 9-12. Wait Mode Entry Timing
WAIT ADDR + 1
Figure 9-12
NEXT OPCODE
shows the timing for wait mode
SAME
System Integration Module (SIM)
SAME
Advance Information
SAME
Low-Power Modes
SAME
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