MC68HC708AS48

Manufacturer Part NumberMC68HC708AS48
DescriptionAdvance Information
ManufacturerFREESCALE [Freescale Semiconductor, Inc]
MC68HC708AS48 datasheet
 


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Page 136/396

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System Integration Module (SIM)
9.6 Program Exception Control
Normal, sequential program execution can be changed in three different
ways:
9.6.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register
contents on the stack and sets the interrupt mask (I bit) to prevent
additional interrupts. At the end of an interrupt, the RTI instruction
recovers the CPU register contents from the stack so that normal
processing can resume.
Figure 9-10
Interrupts are latched, and arbitration is performed in the SIM at the start
of interrupt processing. The arbitration result is a constant that the CPU
uses to determine which vector to fetch. Once an interrupt is latched by
the SIM, no other interrupt can take precedence, regardless of priority,
until the latched interrupt is serviced or the I bit is cleared.
(See
MODULE
INTERRUPT
LAST
IAB
SP
ADDRESS
END OF
PC – 1
IDB
LAST INSTR.
LOW BYTE
R/W
Advance Information
136
Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
Reset
Break interrupts
Figure 9-8
shows interrupt recovery timing.
Figure
9-9.)
SP – 1
SP – 2
SP – 3
SP – 4
PC – 1
X
A
HIGH BYTE
Figure 9-8. Interrupt Entry Timing
System Integration Module (SIM)
shows interrupt entry timing.
VECTOR
VECTOR
NEW PC
NEW PC
ADDR. HIGH
ADDR. LOW
VECTOR
VECTOR
CCR
OPCODE
HIGH
LOW
MC68HC708AS48
Rev. 4.0
MOTOROLA
+ 1