MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 362

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Byte Data Link Controller–Digital (BDLC–D)
Advance Information
362
IE— Interrupt Enable Bit
WCM — Wait Clock Mode Bit
This bit determines whether the BDLC will generate CPU interrupt
requests in run mode. It does not affect CPU interrupt requests when
exiting the BDLC stop or BDLC wait modes. Interrupt requests will be
maintained until all of the interrupt request sources are cleared by
performing the specified actions upon the BDLC’s registers. Interrupts
that were pending at the time that this bit is cleared may be lost.
If the programmer does not wish to use the interrupt capability of the
BDLC, the BDLC state vector register (BSVR) can be polled
periodically by the programmer to determine BDLC states. See
BDLC State Vector Register
This bit determines the operation of the BDLC during CPU wait mode.
See
use.
f
1 = Enable interrupt requests from BDLC
0 = Disable interrupt requests from BDLC
1 = Stop BDLC internal clocks during CPU wait mode
0 = Run BDLC internal clocks during CPU wait mode
XCLK
Byte Data Link Controller–Digital (BDLC–D)
20.8.2 Stop Mode
1.049 MHz
2.097 MHz
4.194 MHz
8.389 MHz
1.000 MHz
2.000 MHz
4.000 MHz
8.000 MHz
Frequency
Table 20-3. BDLC Rate Selection
R1
and
0
0
1
1
0
0
1
1
20.8.1 Wait Mode
for a description of the BSVR.
R0
0
1
0
1
0
1
0
1
Division
MC68HC708AS48
1
2
4
8
1
2
4
8
for more details on its
1.049 MHz
1.049 MHz
1.049 MHz
1.049 MHz
1.00 MHz
1.00 MHz
1.00 MHz
1.00 MHz
f
MOTOROLA
BDLC
—
Rev. 4.0
20.7.4