MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 291

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

18.6.2 Transmission Format When CPHA = 0
MC68HC708AS48
MOTOROLA
CAPTURE STROBE
FOR REFERENCE
FROM MASTER
SCK CPOL = 0
SCK CPOL = 1
SCK CYCLE #
SS TO SLAVE
FROM SLAVE
MOSI
MISO
—
Rev. 4.0
Figure 18-4. Transmission Format (CPHA = 0)
Figure 18-4
logic 0. The figure should not be used as a replacement for data sheet
parametric information.Two waveforms are shown for SCK: one for
CPOL = 0 and another for CPOL = 1. The diagram may be interpreted
as a master or slave timing diagram since the serial clock (SCK), master
in/slave out (MISO), and master out/slave in (MOSI) pins are directly
connected between the master and the slave. The MISO signal is the
output from the slave, and the MOSI signal is the output from the master.
The SS line is the slave select input to the slave. The slave SPI drives
its MISO output only when its slave select input (SS) is at logic 0, so that
only the selected slave drives to the master. The SS pin of the master is
not shown but is assumed to be inactive. The SS pin of the master must
be high or must be reconfigured as general-purpose I/O not affecting the
SPI. (See
edge is the MSB capture strobe. Therefore, the slave must begin driving
its data before the first SPSCK edge, and a falling edge on the SS pin is
used to start the transmission. The SS pin must be toggled high and then
low again between each byte transmitted as shown in
MSB
MSB
1
18.7.2 Mode Fault
BIT 6
BIT 6
Serial Peripheral Interface (SPI)
2
shows an SPI transmission in which CPHA (SPCR) is
BIT 5
BIT 5
3
BIT 4
BIT 4
4
Error.) When CPHA = 0, the first SPSCK
BIT 3
BIT 3
5
BIT 2
BIT 2
6
Serial Peripheral Interface (SPI)
BIT 1
BIT 1
7
Transmission Formats
Advance Information
Figure
LSB
LSB
8
18-5.
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