MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 112

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Clock Generator Module (CGM)
8.6.1 PLL Control Register
Advance Information
112
NOTE:
Address:
The PLL control register contains the interrupt enable and flag bits, the
on/off switch, and the base clock selector bit.
PLLIE — PLL Interrupt Enable Bit
PLLF — PLL Flag Bit
Do not inadvertently clear the PLLF bit. Any read or read-modify-write
operation on the PLL control register clears the PLLF bit.
Reset:
Read:
Write:
This read/write bit enables the PLL to generate an interrupt request
when the LOCK bit toggles, setting the PLL flag, PLLF. When the
AUTO bit in the PLL bandwidth control register (PBWC) is clear,
PLLIE cannot be written and reads as logic 0. Reset clears the PLLIE
bit.
This read-only bit is set whenever the LOCK bit toggles. PLLF
generates an interrupt request if the PLLIE bit also is set. PLLF
always reads as logic 0 when the AUTO bit in the PLL bandwidth
control register (PBWC) is clear. Clear the PLLF bit by reading the
PLL control register. Reset clears the PLLF bit.
1 = PLL interrupts enabled
0 = PLL interrupts disabled
1 = Change in lock condition
0 = No change in lock condition
$001C
PLLIE
Bit 7
R
0
Clock Generator Module (CGM)
Figure 8-5. PLL Control Register (PCTL)
= Reserved
PLLF
R
6
0
PLLON
5
1
BCS
4
0
R
3
1
1
MC68HC708AS48
R
2
1
1
R
1
1
1
MOTOROLA
—
Rev. 4.0
Bit 0
R
1
1