MC68HC708AS48

Manufacturer Part NumberMC68HC708AS48
DescriptionAdvance Information
ManufacturerFREESCALE [Freescale Semiconductor, Inc]
MC68HC708AS48 datasheet
 
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Page 173/396

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The COP counter is a free-running 6-bit counter preceded by the 12-bit
system integration module (SIM) counter. COP timeouts are determined
strictly by the CGM crystal oscillator clock signal (CGMXCLK), not the
CGMOUT signal (see
If not cleared by software, the COP counter overflows and generates an
asynchronous reset after 8,176 or 262,128 CGMXCLK cycles,
depending upon COPL bit in the CONFIG register ($001F) (See
Configuration
With a 4.9152-MHz crystal and the COPL bit in the CONFIG register
($001F) set to a logic 1, the COP timeout period is approximately
53.3 ms. Writing any value to location $FFFF before overflow occurs
clears the COP counter, clears bits 12 through 4 of the SIM counter, and
prevents reset. A CPU interrupt routine can be used to clear the COP.
NOTE:
The COP should be serviced as soon as possible out of reset and before
entering or after exiting stop mode to guarantee the maximum selected
amount of time before the first timeout.
A COP reset pulls the RST pin low for 32 CGMXCLK cycles and sets the
COP bit in the SIM reset status register (SRSR) (see
Register).
While the microcontroller is in monitor mode, the COP module is
disabled if the RST pin or the IRQ/V
5.0 Volt DC Electrical
V
HI
NOTE:
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
MC68HC708AS48
Rev. 4.0
MOTOROLA
Figure 8-1. CGM Block
Register.)
COP timeout period = 8,176 or 262,128 / f
Characteristics). During a break state, V
on the RST pin disables the COP module.
Computer Operating Properly (COP)
Computer Operating Properly (COP)
Functional Description
Diagram).
osc
9.8.2 Reset Status
pin is held at V
+ V
(see
PP
DD
HI
Advance Information
5.4
21.5
+
DD
173