MC68HC708AS48 FREESCALE [Freescale Semiconductor, Inc], MC68HC708AS48 Datasheet - Page 217

• Manufacturer Part Number: MC68HC708AS48
• Description: Advance Information
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MC68HC708AS48
MOTOROLA
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Rev. 4.0
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization.
The free-running counter contents are transferred to the TIM channel
status and control register (TSC0–TSC5, see
Status and Control
regardless of whether the TIM channel flag (CH0F–CH5F in
TSC0–TSC5 registers) is set or clear. When the status flag is set, a CPU
interrupt is generated if enabled. The value of the count latched or
“captured” is the time of the event. Because this value is stored in the
input capture register when the actual event occurs, user software can
respond to this event at a later time and determine the actual time of the
event. However, this must be done prior to another input capture on the
same pin; otherwise, the previous time value will be lost.
By recording the times for successive edges on an incoming signal,
software can determine the period and/or pulse width of the signal. To
measure a period, two successive edges of the same polarity are
captured. To measure a pulse width, two alternate polarity edges are
captured. Software should track the overflows at the 16-bit module
counter to extend its range.
Another use for the input capture function is to establish a time
reference. In this case, an input capture function is used in conjunction
with an output compare function. For example, to activate an output
signal a specified number of clock cycles after detecting an input event
(edge), use the input capture function to record the time at which the
edge occurred. A number corresponding to the desired delay is added
to this captured value and stored to an output compare register (see
16.9.5 TIM Channel
output compares are referenced to the same 16-bit modulo counter, the
delay can be controlled to the resolution of the counter independent of
software latencies.
Reset does not affect the contents of the input capture register.
Timer Interface (TIM)
Registers) on each proper signal transition
Registers). Because both input captures and
16.9.4 TIM Channel
Functional Description
Timer Interface (TIM)
Advance Information
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