MC68HC708AS48

Manufacturer Part NumberMC68HC708AS48
DescriptionAdvance Information
ManufacturerFREESCALE [Freescale Semiconductor, Inc]
MC68HC708AS48 datasheet
 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
Page 111
112
Page 112
113
Page 113
114
Page 114
115
Page 115
116
Page 116
117
Page 117
118
Page 118
119
Page 119
120
Page 120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
Page 120/396

Download datasheet (4Mb)Embed
PrevNext
Clock Generator Module (CGM)
is the time taken to return from 900 kHz to 1 MHz 5 kHz. Five kHz = 5%
of the 100-kHz step input.
Other systems refer to acquisition and lock times as the time the system
takes to reduce the error between the actual output and the desired
output to within specified tolerances. Therefore, the acquisition or lock
time varies according to the original error in the output. Minor errors may
not even be registered. Typical PLL applications prefer to use this
definition because the system requires the output frequency to be within
a certain tolerance of the desired frequency regardless of the size of the
initial error.
The discrepancy in these definitions makes it difficult to specify an
acquisition or lock time for a typical PLL. Therefore, the definitions for
acquisition and lock times for this module are as follows:
Obviously, the acquisition and lock times can vary according to how
large the frequency error is and may be shorter or longer in many cases.
Advance Information
120
Acquisition time, t
, is the time the PLL takes to reduce the error
ACQ
between the actual output frequency and the desired output
frequency to less than the tracking mode entry tolerance,
Acquisition time is based on an initial frequency error, [(f
f
)/f
], of not more than 100%. In automatic bandwidth
ORIG
DES
control mode (see
8.4.2.3 Manual and Automatic PLL
Bandwidth
Modes), acquisition time expires when the ACQ bit
becomes set in the PLL bandwidth control register (PBWC).
Lock time, t
, is the time the PLL takes to reduce the error
LOCK
between the actual output frequency and the desired output
frequency to less than the lock mode entry tolerance,
time is based on an initial frequency error, [(f
more than 100%. In automatic bandwidth control mode, lock time
expires when the LOCK bit becomes set in the PLL bandwidth
control register (PBWC). (See
PLL Bandwidth
Modes.)
Clock Generator Module (CGM)
TRK
DES
. Lock
LOCK
– f
)/f
], of not
DES
ORIG
DES
8.4.2.3 Manual and Automatic
MC68HC708AS48
Rev. 4.0
MOTOROLA
.